Exemplary embodiments relate to the high voltage switch circuit of a semiconductor device and, more particularly, to the high voltage switch circuit of a semiconductor device, which is capable of performing a normal operation even when an internal voltage becomes a low voltage level.
An exemplary semiconductor device including a high voltage switch circuit, from among semiconductor devices, is described below.
The semiconductor device includes a controller for outputting a high voltage switch enable signal in response to an address, a plurality of high voltage switch circuits for outputting a block selection signal in response to the high voltage switch enable signal, and a plurality of block switches for transferring a high voltage to a selected memory cell block in response to the block selection signal.
When a high voltage switch circuit selected from among the high voltage switch circuits is activated and the remaining unselected high voltage switch circuits are inactivated, the activated high voltage switch circuit may output the block selection signal of a high level, and the unselected high voltage switch circuits may output the block selection signal of a low level.
Recently, in order to reduce a voltage drop of the block selection signal which is an output signal of the high voltage switch circuit, the high voltage switch circuit consists of a high voltage transistor and a negative transistor having a negative threshold voltage.
More particularly, the high voltage switch circuit includes a boost circuit for outputting the block selection signal of a high voltage when the high voltage switch circuit is activated. The boost circuit may include the negative transistor and the high voltage transistor coupled in series. The high voltage transistor may be a high voltage PMOS transistor, and the negative transistor may be a negative NMOS transistor.
Here, when the high voltage switch circuit is activated, the high voltage PMOS transistor is turned on, and when the high voltage switch circuit is inactivated, the high voltage PMOS transistor is turned off. That is, when the high voltage PMOS transistor is turned on, the feedback loop of the boost circuit becomes formed and so a level of the block selection signal rises, and when the high voltage PMOS transistor is turned off, the feedback loop is not formed and so an output node is discharged. Accordingly, the block selection signal of a low level is outputted.
Meanwhile, in order to fully turn off the high voltage PMOS transistor, a sufficiently high level voltage is supplied to the gate of the high voltage PMOS transistor. However, if the level of the turn-on voltage becomes lowered (for example, the level of the internal voltage becomes lowered), the high voltage PMOS transistor may be slightly turned on, and so a channel may be formed. That is, the voltage level of a source of the high voltage PMOS transistor may rise. The source of the high voltage PMOS transistor is coupled to the gate of the negative NMOS transistor so that the feedback loop is formed. Thus, if the voltage level of a source of the high voltage PMOS transistor rises, the turn-on voltage of the negative NMOS transistor also rises. Accordingly, the feedback loop may be formed in operations in which the feedback loop should not be formed, and so the high voltage switch circuit may not perform a normal operation. Consequently, reliability of the high voltage switch circuit may be deteriorated in a low voltage level.